The present invention relates generally to scanning electron microscope (SEM) systems that can automatically acquire images of any evaluation point on a specimen and evaluate a circuit pattern formed at the evaluation point, and to methods using the SEM systems. More particularly, the invention concerns a SEM system having an imaging recipe and measuring recipe auto-creating function which determines an imaging recipe and measuring recipe constructed to allow acquisition of a SEM image of any evaluation point and desired evaluation for this point (e.g., measurement of line pattern wiring widths or line pattern gaps and extraction of image feature quantities of a defective region). The imaging recipe and measuring recipe is determined from circuit pattern design data automatically and without using an actual wafer. The invention also concerns a method that uses the above SEM system.
A wiring pattern is formed on a semiconductor wafer by applying a coating material, called the resist, to the surface of the semiconductor wafer, then stacking a wiring pattern exposure mask (reticule) upon the resist, and emitting radiation such as a visible ray, ultraviolet ray, or electron beam, from above the mask. Thus, the resist is photosensitized and the wiring pattern is formed. Since the thus-obtained wiring pattern changes in shape according to the intensity or diameter of the visible ray, ultraviolet ray, or electron beam emitted, the finished state of the pattern needs inspecting to form a more precise wiring pattern. A critical-dimension scanning electron microscope (CD-SEM) has traditionally been used for such inspection. The critical point (hot spot) on the semiconductor pattern which requires inspection can be detected by exposure simulation or the like. The pattern is observed through SEM with the hot spot as an evaluation point (hereinafter, called the EP), the wiring width and other dimension values of the pattern are measured from an observation image thereof, and the finished state of the pattern is evaluated. Evaluation results are fed back to shape correction of the mask pattern and the manufacturing process parameters for the semiconductor in order to achieve a high yield.
In order to obtain higher EP image quality with a minimum shift in imaging position, part or all of four adjusting points, namely, an addressing point (hereinafter, called the AP), an auto-focusing point (likewise, called the AF point), an automatic astigmatism correction point (likewise, called the AST correction point), and an automatic brightness and contrast control point (likewise, called the ABCC point) are first set according to particular requirements. Next, addressing, auto-focusing control, automatic astigmatism correction, and automatic brightness and contrast control are conducted at the respective adjusting points and images of the EP are acquired. The SEM image previously registered as a template at the AP of known coordinates, and the SEM image observed during the actual imaging sequence (this SEM image is referred to as the actual image template) are matched in position, and a shift in the imaging position during this matching step is corrected as the shift in the imaging position during the above addressing step. The above evaluation point (EP) and the adjusting points (the AP, the AF point, the AST correction point, and the ABCC point) are collectively called the imaging point. The position, imaging parameters, and measuring parameters of the EP, the imaging sequence for the EP, the imaging parameters and adjusting methods relating to each adjusting point, and the registered template described above are managed as imaging and measuring recipes, and the SEM conducts imaging and measurements based on the imaging/measuring recipes.
Traditionally, the imaging and measuring recipes have been generated manually by the SEM operator and the generating operations have been labor- and time-consuming tasks. In addition, since determining each adjusting point and registering a template in the imaging and measuring recipes have required imaging the wafer at a low magnification, the generation of the imaging and measuring recipes has been one cause of the decreases in the operation ratio of the SEM system. Furthermore, the number of sections to be evaluated, that is, the number of EPs has explosively increased with the minute and complexity of patterns, so the above manual generation of the imaging and measuring recipes is becoming a non-reality in terms of labor and generating time.
Under such a situation, JP-A-2002-328015, for example, discloses a semiconductor inspection system adapted to determine the AP on the basis of the semiconductor circuit pattern design data expressed in the GDSII format, further extract the data at the AP from the design data, and register the extracted data as the registered template in an imaging/measuring recipe. In the conventional system proposed in above document 2002-328015, the operation ratio of the SEM improves since actual wafer imaging intended only to determine the AP and register the template is not required. In addition, after acquiring a SEM image at the AP (i.e., an actual image template) during an actual imaging sequence, the conventional system can match the actual image template and the registered template of the design data, re-register a SEM image associated with the position of the registered template of the design data, as a template in an imaging/measuring recipe, and use the re-registered SEM image template in an addressing step. Furthermore, the conventional system has a function that automatically detects a distinctive pattern section from the design data and registers the detected pattern section as an AP.